This invention relates generally to techniques for transferring data between two asynchronous systems and, more particularly, to a technique for controlling buffer memories installed between a local area network and a system memory. The system memory will be referred to as a storage device, to avoid confusion with two buffer memories that will shortly be introduced.
In a typical network, data must be received and transmitted at a speed fixed by the network characteristics, and a network user has no control of this speed once a transmission or reception operation is started. When data is received from the network, it is usually transferred to a storage device, through a system bus, to await further processing, but the system bus to which the storage device is connected is, in most systems, shared by other functional modules, such as a central processing unit and various peripheral devices. Therefore, immediate access to the storage device is not guaranteed. The storage device access, through the system bus, is said to have variable latency or delay.
A well known solution to this difficulty is to provide a buffer memory between the network and the system bus. The buffer memory can continue to receive data from the network even when access to the system bus is temporarily denied. When access to the storage device is subsequently granted, the buffer memory is emptied, and "catches up" with the network. There is, of course, the possibility of an overflow condition, when access to the storage device is denied for long enough that the buffer memory becomes completely filled.
A similar difficulty is presented during transmission of data from the storage device to the network. Once network access is granted, data must be sent at a predetermined fixed rate, but the storage device may not always be able to supply data at this rate. Another buffer memory in the transmit path allows a limited amount of data to be supplied to the network even when access to the storage device is temporarily denied. In this case, there is the possibility of buffer memory underflow, when the buffer memory is completely emptied by the demand of data from the network, and access to the storage device continues to be denied.
Traditional designs for managing buffer memories in communication systems have treated transmit and receive operations as completely independent of each other. If a receive operation is in progress, priority is given to completion of the operation, at least until a complete packet of data is received and stored in the storage device. Only then is any attention given to possible transmit operations, but if another receive packet is recognized before the transmit operation begins the transmit operation is aborted. In a busy network, receive operations can completely monopolize the buffer manager's time, and transmission may be delayed indefinitely.
Another approach is to interleave receive and transmit operations on the storage device. This allows a transmission to be ready and able to start even though data transfers due to the receive operation have not been completed. This approach has the advantage that it makes more aggressive use of the network communication channel, but has the disadvantage that it is more prone to overflows and underflows, because it requires the system bus to carry more data in the same amount of time.
What is still needed in this field is a more efficient buffer memory management system, which minimizes or avoids buffer memory overflow and underflow conditions, but provides aggressive sharing of transmit and receive operations with minimum loss of data. An obvious solution is simply to increase the size of the buffer memories until overflow and underflow conditions are reduced to a desired level. However, this increases hardware cost and can impose additional time delays in both the transmit and receive paths.
Another approach is simply to require that the system bus have higher speed or greater "width" (the number of parallel data bits handled by the bus), so that the conflicting requirements for system bus access can be met without significantly improving the buffer management technique. Obviously, this approach also increases hardware costs and is not a completely satisfactory solution either.
It will be appreciated from the foregoing that there is still a need for a more efficient buffer memory management system for use in interfacing between asynchronous components, such as a local area network and a storage device with variable latency. The present invention is directed to this end.